In our semester thesis “Cryptographic Hardware Extension for OpenSSL Library”, Mathias Schnydrig and I developed a AES and SHA implementation on a XILINX Virtex 6 FPGA. The implementatio was done on the Virtex-6 FPGA ML605 Evaluation Kit. Our project was supervised by Christoph Keller and Luca Henzen (Co-author of the SHA-3 finalistBlake“).

At first, we implemented the encryption and hashing algorithm AES-128 OFB (Mathias Schnydrig) and SHA-256 (Benedikt Köppel) in VHDL. On top of these two components, a PCI-Express layer was introduced between the PCI-Express hardware block and our crypto implementations.

On Linux, the Xilinx reference implementation driver as adopted to work with our AES and SHA implementations on hardware. As further project, our Linux driver could now be integrated into the OpenSSL library to speed up encryption and hashing.

The documentation of our project can be found here.

Hardware Evaluation of SHA-3 3rd round candidates

The Integrated Systems Laboratory of the ETH Zurich has conducted a further study, comparing SHA-3 finalists with my SHA-2 implementation. The study can be found at http://www.iis.ee.ethz.ch/~sha3/, my reference implementation of SHA-2 at http://www.iis.ee.ethz.ch/~sha3/ethz_sha2/sourcecode/index.html.